In some power converters, particularly those including isolation transformers, it is mandatory to limit the maximum duty cycle generated by the converter's pulse width modulator.
The duty cycle of the pulse width modulator output signal (which controls power converter "on-time") must be limited to a certain maximum which, to avoid damage or failure, may not be exceeded under any condition; transient or steady state. This possibility for damage is due to the transformer's inability to demagnetize at large duty cycle ratios and it emphasizes the importance of accurately setting the maximum duty cycle value.
FIG. 1(a) illustrates a prior art pulse width modulator as implemented for example by the Unitrode UC3825 high speed PWM controller.
As shown, the Unitrode PWM function is performed by comparator 1 which receives as one input a voltage V.sub.1 derived from an error amplifier (not shown), and as a second input, a sawtooth signal V.sub.2 (illustrated in FIG. 1(b)) which is generated by an oscillator (not shown).
The two inputs cause the output of the PWM comparator to be high as long as the sawtooth voltage V.sub.2 is lower in amplitude than the error voltage V.sub.l, and to be low when the sawtooth voltage V.sub.2 exceeds the voltage V.sub.1.
The duty cycle .delta. is mathematically defined as: ##EQU1## where t.sub.on is the time interval when the output of the PWM comparator is high, and T is the entire period of the signal.
Viewing FIGS. 1(b) and 1(c), the duty cycle .delta. at the output of the Unitrode PWM modulator is varied from zero to unity as the value of the error voltage V.sub.1 varies from less than the lowest value of sawtooth voltage V.sub.2 (i.e. V.sub.valley) to more than the highest value of sawtooth voltage V.sub.2 (i.e., V.sub.peak).
To limit the maximum duty cycle to a value lower than unity, the prior art method limits V.sub.2 by applying a voltage clamp 2 to the PWM comparator input. A circuit implementation of this method is shown in FIG. 1(a) where a diode 3 and adjustable source 2 are used to set a clamp level, V.sub.clamp. A waveform illustrating the method is shown in FIG. 1(c).
Assuming for illustration that the value of V.sub.clamp is made equal to V.sub.peak /2, and that the forward drop of diode 3 is negligible, then under these conditions the Unitrode maximum duty cycle will be limited to 50%.
This method of duty cycle limiting, although simple, is extremely inaccurate. The duty cycle calibration is affected by several factors that vary from circuit to circuit, and also vary for a given circuit as the ambient temperature and the supply voltage of the circuit changes.
These factors include:
Initial accuracy and temperature stability of V.sub.clamp ; PA0 Initial accuracy and supply/temperature stability of V.sub.peak ; PA0 Initial accuracy and supply/temperature stability of V.sub.valley ; PA0 Initial value and supply/temperature stability of the response time of comparator 1. PA0 (a) means for generating a reference PWM signal having a preset duty cycle representing a maximum value; PA0 (b) means for comparing said reference PWM signal with said system PWM signal such that the maximum duty cycle of the latter is determined by that of the former.
The cumulative effect of the above variations may be very significant. They may amount to a sizeable tolerance in the maximum duty cycle setting. Accommodation of this tolerance requires trade offs in the design of the converters that adversely affect performance parameters such as power density, efficiency and cost.
It is therefore one object of this invention to provide an improved technique in power conversion circuits for limiting the maximum duty cycle of a pulse width modulator to an accurate value.
It is still a further object of the present invention to provide accurate PWM duty cycle limiting circuits which vary within close tolerances from circuit to circuit.
It is yet a further object of the present invention to provide an accurate PWM duty cycle limiter which is virtually unaffected by temperature and circuit voltage changes.